This invention relates to circuits and methods for detecting a lock condition of a phase-locked loop (PLL) circuit. More particularly, this invention relates to circuits and methods for detecting a PLL lock condition using digital components.
PLL circuits are widely used in many clock recovery applications. Typically, a PLL circuit locks (i.e., synchronizes) a clock output by a voltage-controlled oscillator (VCO) to a reference clock. An associated PLL lock detector outputs a LOCK signal indicating when the VCO clock is locked. When the PLL lock detector outputs the LOCK signal, the VCO clock is used to control one or more processes of an associated device or chip. In this way, the processes of the device or chip are synchronized to the reference clock. Synchronization to a reference clock is important, for example, in high-speed memory devices in which memory device processing must rigidly comply with precise timing requirements.
Conventional lock detectors use an analog low pass filter (i.e., integrator) and an analog comparator to detect a lock condition of an associated PLL circuit. Such PLL lock detectors are described in Tan et al. U.S. Pat. No. 6,580,328, issued Jun. 17, 2003. It is well-known that analog designs are more difficult to mass produce reliably within stated specifications and are less portable to various process technologies than digital designs.
In view of the foregoing, it would be desirable to provide circuits and methods for detecting a lock condition of a PLL circuit that rely less on analog components and more on digital components.